1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof. Specifically, the present invention relates to a semiconductor device in which an LDD (Lightly Doped Drain) region is formed in a self-aligning manner and a manufacturing method thereof.
2. Description of the Related Art
Recently, in the field of an image display device, the development of a system-on-panel incorporating logic circuits such as a memory circuit and a clock generating circuit, in addition to a pixel or a driver circuit, on an insulating substrate having transparence e.g. glass or quartz, has attracted attention. The technical development of manufacturing a TFT with high switching speed on an insulating substrate having transparence is required to realize high-speed operation for driver circuits and logic circuits. A TFT with high switching speed is manufactured by using a semiconductor film with fewer crystal defects and by miniaturizing an element size.
Even if an element size is miniaturized proportionally, drive voltage cannot always be reduced proportionally in order to keep signal speed and response speed. Consequently, the vicinity of a drain region becomes high electric field by miniaturizing an element size of a MOS transistor. Accordingly, electrons and holes having high energy, which are referred to hot carriers, are generated and caught in a gate insulating film. And it is known that this will cause a degradation phenomenon such as fluctuation in a threshold voltage.
It is effective to apply an LDD (Lightly Doped Drain) structure as an element structure. The LDD structure is formed by providing a low concentration impurity region in a drain end which is in contact with a channel. As low concentration impurities, an n-type impurity is used in the case of an n-channel element, while a p-type impurity is used in the case of a p-channel element. In this manner, electric field in the vicinity of the drain region is relaxed and the generation of hot carriers is controlled by making an impurity concentration gradient in the channel-drain junction. (For example, described in page 201–207 in “Novel fundamental of semiconductor device” written by S. Kishino, printed by Ohmsha, Ltd in year of 1995)
A degradation phenomenon caused by hot carriers is generated not only in a MOS transistor but also in a TFT. And it can be also prevented by applying an LDD structure as an element structure of a TFT as well as that of a MOS transistor.
The formation method of a general LDD structure in MOS transistor is described with reference to FIGS. 1A to 1D. However, the process through device isolation and the process after the formation of an LDD region are omitted here.
A gate insulating film 103 is formed on a semiconductor film 102 with device isolation. A gate electrode 104 made of polysilicon is formed on the gate insulating film 103. After forming the gate electrode 104 into a desired shape, ions at low concentration are doped into the semiconductor film 102. Next, a silicon oxide film 105 with isotropic step coverage is formed on the gate electrode 104. Then, sidewalls 106 are formed by performing anisotropic etching in vertical direction to leave the silicon oxide 105 only on the sidewalls of the gate electrode. A source and a drain regions 108 are formed by doping ions at high concentration in the semiconductor film 102 so that ions do not penetrate the sidewalls 106. The ions at high concentration are not doped into lower portions of the sidewalls 106, and then the lower portions of the sidewalls 106 are to be LDD regions 107.
As described above, an LDD region is formed in a self-aligning manner by using a sidewall without patterning. With miniaturization in an element size, there is a case in which alignment accuracy is required in a submarginal of the accuracy in a patterning process (approximately ±0.2 μm). In this case, an LDD region can be formed with higher accuracy in a self-aligning manner, instead of patterning. Hence, the above-described method is used when alignment accuracy is higher in the case of using a self-aligning manner in the formation of an LDD region.
An LDD region can be formed in a TFT by the same way as in a MOS transistor. However, since an insulating material such as a quartz substrate is used for forming a TFT, the TFT is easily to be charged and damaged by plasma especially in anisotropic etching to form sidewalls. In the element damaged by plasma, electrical charges in a gate insulating film and energy level in an interface between a semiconductor layer and a gate insulating layer are generated, and, as a result, deterioration such as fluctuation in threshold voltage is caused.
FIG. 2A shows a relationship between channel lengths of TFTs formed on a quartz substrate and threshold voltages thereof. According to FIG. 2A, when the channel length is 1 μm or less, the threshold voltage drops to a minus value, as low as 10 V is caused.
It is considered that such damage by plasma generated in the formation process of an LDD region is resulted from the difficulty in discharging electric charge accumulated in a gate electrode of which surface area is reduced by processing into a desired shape, and results in having serious impact on an element characteristic. Therefore, a good deal of damage by plasma is caused, since the charge density which is to be accumulated in the gate electrode increase, as the surface area of the gate electrode is reduced by miniaturization of an element size and as the thickness of the gate insulating film is reduced. Damage by electric charged accumulated in a gate electrode which is miniaturized in the case of doping charged particles, in the same way as the case of anisotropic etching.
However, the miniaturization of an element size is required more and more in order to manufacture TFTs with high switching speed which is essential for an element of logic operation circuit, and in order to obtain a higher integration. Accordingly, the development of manufacturing method of TFTs having LDD structures, which can take advantage of self aligning manner having high manufacturing accuracy and decrease the damage by the plasma and doping process as much as possible is needed.